1. Field of the Invention
Embodiments of the present invention generally relates to semiconductor processing technologies and, more specifically, to improved methods for fabricating a damascene structure without damaging low-k dielectric materials in the structure.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The demand for greater circuit density necessitates a reduction in the dimensions of the integrated circuit components, e.g., sub-micron dimensions and the use of various materials to fabricate devices in order to achieve much faster and better electrical performance, such as materials with higher conductivity used in metal lines, materials with lower permittivity (low-k) dielectric constant used as insulating materials, etc. For integrated circuit fabrication, metal interconnects with low resistance, such as copper and aluminum interconnects, provide conductive paths between the integrate circuit components on integrated circuit devices. Generally, metal interconnects are electrically isolated from each other by a dielectric bulk insulating material. At sub-micron dimensions, capacitive coupling potentially occurs between adjacent metal interconnects, which may cause cross talk and/or resistance-capacitance (RC) delay and degrade the overall performance of the integrated circuit.
One method for forming vertical and horizontal interconnects for the integrated circuit components is by a damascene or dual damascene method. Typically, damascene structures have dielectric bulk insulating layers and conductive metal layers, such as low dielectric constant materials and conductive copper layers, stacked on top of one another. Vertical interconnects, i.e., vias, and horizontal interconnects, i.e., trenches are etched into the dielectric bulk insulating layer and the conductive metal layers are subsequently filled into the vias and/or trenches and planarized, such as by a chemical mechanical planarization process (CMP), so that the conducting metal materials are only left in the vias and/or trenches. In the damascene approach, a rather complex dielectric film stack that includes a sequence of hard mask, low-k dielectrics, and etch stop layers, etc., may be required. To obtain such a stack, via/trench lithography, patterning, and wet cleanings are typically required before filing the vias and the trenches with the conductive metal materials.
However, low-k materials of the damascene structure are susceptible to various damages during subsequent processing steps, such as etching, wet-cleaning, pre-metal cleaning, or CMP etc. Such damages can severely increase the dielectric constant of the low-k materials, causing the overall dielectric constant of the resulting dielectric film stack to increase.
Therefore, there is a need for a process of making damascene structures with zero or minimized damages to low-k materials in the dielectric film stack.